DS200DSPCH1ADA is a Digital Signal Processor Control Board manufactured and designed by General Electric as part of the Mark V Series used in GE Speedtronic Control Systems. The DS200DSPC board (DSPC) is a high-performance processor board based on a digital signal processor that provides computational capacity and communications bandwidth for direct control of high-performance power converters applications such as uninterruptable power sources (UPS), active filters, dynamometers, wind turbines, high performance drives, and large multi-bridge power converters. The board plugs into one slot of a VME rack but occupies two slots of space (for the quantity of one to four daughterboards). The DSPC board can serve as a master or slave device, yet it provides its program memory and expandable local high speed I/O for direct interface to control signals without using the VME datapath.
DS200DSPCH1ADA Technical Specifications
| Part Number: | S200DSPCH1ADA |
| Manufacturer: | General Electric |
| Series: | Mark V |
| Product Function: | Digital Signal Processor Control Board |
| Power Requirements: | +5 V dc, 6 A |
| Number of relay channels: | 12 |
| Trip Solenoid Rating: | 125 V dc |
| Power supply voltage: | 28 V dc |
| Voltage Range: | 18 - 32 VDC |
| Mounting Option: | DIN-rail mounting |
| Operating temperature: | -30 to +65 degrees Celsius |
Characteristic
- The DSPC board provides optional VME bus interface connectors (P1 and P2) that are compatible with the GE Fanuc 90/70 Programmable Logic Controllers (PLCs). The DSPC board can function as an A24/D16 VME bus slave with an 8K dual-ported SRAM interface.
- The board can also function as a VME bus master to initiate a bus transfer cycle, including bus arbitration. VME bus access is controlled in a configurable static random access memory (SRAM) based field programmable gate array (FPGA) device.
- Bus interface configuration information resides in a programmable logic device that can be reconfigured as required for a specific application (this method minimizes manual jumpers). VME bus I/O is asynchronous and a timeout is provided for non- responding addresses.
- Program and FPGA logic configuration data is stored in flash memory on a removable SIMM, while configurable items for applications are stored in a socket-mounted EEPROM. Program code is executed from high-speed static RAM after startup.
- Flash EPROM facilitates the downloading and updating of the application's real-time code and erasable programmable logic device (EPLD) logic. Logic is concentrated in a combination of SRAM-based FPGAs and EPLD programable logic devices.
- Surface-mounted in-circuit programmable devices are used for the ready generation, chip selection, and boot control logic (these devices are programmed by an in-system programmable [ISP] serial interface).
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